Product Summary
The 74HC174D is a Hex D-type flip-flop with reset positive-edge trigger. The 74HC174D is a high-speed Si-gate CMOS device and is a pin compatible with low power Schottky TTL (LSTTL). The 74HC174D is specified in compliance with JEDEC standard no. 7A.
Parametrics
74HC174D absolute maximum ratings: (1)tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V CP to Qn: 17 ns; (2)MR to Qn: 13 ns; (3)fmax maximum clock frequency: 99 MHz; (4)CI input capacitance: 3.5 pF; (5)CPD power dissipation capacitance per flip-flop: 17 pF.
Features
74HC174D features: (1)Six edge-triggered D-type flip-flops; (2)Asynchronous master reset; (3)Output capability: standard; (4)ICC category: MSI.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
Quantity | |||||||||||||
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74HC174D |
NXP Semiconductors |
Flip Flops HEX D F-F POS-EDGE W/RESET |
Data Sheet |
Negotiable |
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74HC174D,652 |
NXP Semiconductors |
Flip Flops HEX D F-F POS-EDGE |
Data Sheet |
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74HC174D,653 |
NXP Semiconductors |
Flip Flops HEX D-TYPE MASTER RESET |
Data Sheet |
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74HC174DB,118 |
NXP Semiconductors |
Flip Flops HEX D-TYPE MASTER |
Data Sheet |
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74HC174DB,112 |
NXP Semiconductors |
Flip Flops HEX D-TYPE MASTER |
Data Sheet |
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74HC174DB |
NXP Semiconductors |
Flip Flops HEX D-TYPE MASTER RESET |
Data Sheet |
Negotiable |
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74HC174DB-T |
NXP Semiconductors |
Flip Flops HEX D-TYPE MASTER RESET |
Data Sheet |
Negotiable |
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